NICE Conference Series

There are many intriguing proposals for next-generation efficient computing substrates, and Biologically-inspired neuromorphic platforms are one such alternative. We have previously participated in the development of asynchronous hardware for a number of neuromorphic substrates, but compelling evidence for neuromorphic systems is still absent. We discuss the current state of our effort in creating both software and hardware infrastructure for the co-design of algorithms and hardware for neuromorphic systems.

In 2021 Wunderlich and Pehle published the “Eventprop” method of using the adjoint method to calculate exact gradients in spiking neural networks (SNNs) of LIF neurons, and used the method to solve diagnostic machine learning benchmarks such as the YinYang dataset and latency MNIST. Soon after, we were able to show that this work could be extended to problems such as keyword recognition on the SHD and SSC benchmarks and to networks with delays and for learning delays. The trained networks run on Intel’s Loihi with minimal accuracy loss and considerable energy savings.

Pehle’s PhD thesis also contains more general equations for any hybrid SNN models. Based on this, we have used Python’s sympy symbolic math package to implement an “auto-adjoint” method in our mlGeNN software, not unlike the powerful “autodiff” methods in PyTorch, TensorFlow or JAX. This allows users to define neuron and synapse models of their choice, which mlGeNN automatically turns into equations and code for gradient descent on the chosen model. However, there are issues that mean that adjoint learning in SNNs is not yet as plug and play as autodiff-based error backpropagation in time in artificial neural networks.

In this talk, I will briefly introduce the overall method and will then discuss the main advances and the challenges for a wider adoption of this technology, drawing on examples from our recent works.

Jonathan Timcheck, Alessandro Pierro and Sumit Bam Shrestha

Neuromorphic hardware promises major gains in speed and energy efficiency, but designing fast kernels is hindered by the lack of simple, predictive performance models. In this talk, we present the first max‑affine (multi‑dimensional roofline) runtime model for Intel’s Loihi 2 that captures both compute and on‑chip communication costs. Calibrated using microbenchmarks, the model shows a tight match to measured runtimes (≥ 0.97 Pearson correlation) for matrix‑vector multiplication and a QUBO solver. We further use the model to analyze communication bottlenecks and scalability, revealing clear area–runtime tradeoffs. This work enables principled, performance‑driven algorithm design on Loihi 2.

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Jakob Kaiser, Eric Müller and Johannes Schemmel

Mapping experimental observations to parameters of analog neuromorphic hardware is often labor-intensive. We apply amortized simulation-based inference to infer parameters of an adaptive exponential integrate-and-fire neuron implemented on the BrainScaleS-2 system. Using membrane potential responses to step current stimulation, we estimate posterior distributions for seven model parameters. We compare different approaches for extracting summary statistics from membrane traces and evaluate their impact on inference performance. Our results demonstrate that amortized SBI is a promising tool for parameterizing analog neuron circuits.

Jack Klawitter and Konstantinos P. Michmizos

Spiking neural networks (SNNs) have emerged as a compelling alternative to standard artificial neural networks (ANNs) due to their biological plausibility and energy efficiency. However, while feature attribution methods are well established for ANNs, comparable techniques for SNNs remain underdeveloped. Here, I introduce Critical Spike Attribution (CSA), a causal attribution method that identifies which presynaptic spikes were functionally necessary for producing downstream firing. CSA provides temporally resolved explanations and is compatible with any training method. CSA is evaluated on both the Spiking Heidelberg Digits dataset and a real-world neural decoding task. Across both settings, CSA more accurately identifies causal features while producing sparser explanations with minimal trade-off in completeness.

Ming-Jay Yang, Dimitrios Spithouris, Johannes Hellwig, Pascal Nieters, Regina Dittmann, Gordon Pipa and John Paul Strachan

In-memory computing (IMC) with memristive cross-bar arrays offers a promising solution to the energy and latency limitations of conventional von Neumann architectures. However, most existing IMC systems rely on perceptron-based neurons, limiting computational flexibility and requiring large, dense networks to achieve competitive performance. Inspired by the nonlinear processing of biological dendrites, this work introduces a hardware-efficient IMC architecture, ”DARWIN”, that integrates nonvolatile memristive devices as synaptic weights arranged as a tree with volatile memristive devices functioning as integration filters. To further optimize hardware utilization, we incorporate learnable sparsity, enabling the network to automatically discover a compact synaptic pattern within a dendritic tree tailored to the underlying device characteristics. Experimental results demonstrate that the proposed architecture achieves more than two orders of magnitude lower memory footprint and at least an order of magnitude lower power consumption than other in-memory computing architectures. These findings highlight the potential of combining dendritic computation, heterogeneous memristive technologies, and sparsity-aware learning to advance scalable and bio-inspired in-memory computing hardware.

Kecheng Zhang, Anders Lansner, Ahsan Javed Awan, Naresh Balaji Ravichandran and Pawel Herman

We propose a neuromorphic solver for the NP-hard Edge User Allocation problem using an attractor network with Winner-Takes-All (WTA) mechanism implemented with the Bayesian Confidence Propagation Neural Network (BCPNN) framework. Unlike previous energy-based attractor networks, our solver uses dynamic heuristic biasing to guide allocations in real time and introduces a “no allocation” state to each WTA motif, achieving near-optimal performance with an empirically upper-bounded number of time steps. The approach is compatible with neuromorphic architectures and may offer improvements in energy efficiency.

Graeme Damberger, Omar Alejandro Garcia Alcantara, Eduardo S. Espinoza, Luis Rodolfo Garcia Carrillo, Terrence C. Stewart and Chris Eliasmith

William Chapman, Darby Smith, Corinne Teeter and Nicole Jackson

Predicting large-scale spatiotemporal data poses significant challenges for traditional machine learning methods, particularly in high-performance and edge-based computing environments. Graph neural networks (GNNs) have emerged as powerful tools for modeling structured data, while reservoir computing (RC) offers efficient and state-of-the-art solutions for predicting low-rank dynamical systems. In this work, we propose a novel approach that integrates the global structured modeling capabilities of GNNs with the efficient training and predictive strengths of RC. By combining local random connectivity with global domain-informed structure, the proposed graph reservoir networks leverage both random and model-based information to accurately predict large-scale spatiotemporal dynamics. Furthermore, we demonstrate the robustness of these networks to neuromorphic hardware constraints, including temporally sparse spiking activity, quantized weights, limited fan-in, and local learning rules. These results highlight the utility of integrating reservoir computing with domain-informed inductive biases, paving the way for scalable and efficient solutions to complex dynamical systems in diverse applications.

Sungmin Lee

Spiking Neural Networks (SNNs) have emerged as a promising energy-efficient alternative to conventional deep learning models. However, realizing truly energy-efficient artificial intelligence requires a synergistic approach that optimizes both the learning algorithm and the underlying hardware architecture. In this talk, we present a novel hardware-algorithm co-design that integrates the SOLO (Spatial Online Learning at Once) algorithm with a novel analog flash device. Specifically, SOLO overcomes the high latency and memory costs of traditional BPTT, enabling highly efficient, noise-robust on-chip training of deep SNNs. By leveraging co-integrated flash devices to model synapses, neurons, and surrogate gradients, we demonstrate a highly efficient and superior platform for analog in-memory computing (AIMC).

Bradley H. Theilman and James B. Aimone

The potential for neuromorphic computing to provide intrinsically fault-tolerant has long been speculated, but demonstrations of brain-like robustness in neuromorphic applications is rare. Here, we show that a previously-described, natively spiking neuromorphic algorithm for solving partial differential equations is intrinsically tolerant to structural perturbations in the form of ablated neurons and dropped spikes. The tolerance band for these perturbations is large: we find that as many as 32% of the neurons and up to 90% of the spikes may be entirely dropped before a significant degradation in the accuracy results. Furthermore, this robustness is tunable through structural hyperparameters. This work demonstrates that the specific brain-like inspiration behind the algorithm contributes to a significant degree of robustness as expected from brain-like neuromorphic algorithms.

Max Hawkins, Richard Vuduc

Neuromorphic computers challenge traditional definitions of computing performance by prioritizing characteristics like sparsity and noise tolerance, which are often ignored by conventional metrics. As a result, the community lacks a fair method of comparing computational work performed by sparse, noisy neurons against dense, deterministic arithmetic logic units (ALUs). We propose a performance framework grounded in information theory that models any computational unit as a channel, transforming and retaining information from inputs (X) to outputs (Y). By defining computing ‘work’ as the mutual information, I(X; Y), between input and output states, we provide an implementation-agnostic framework for computational performance. This framework resolves conflicting definitions of work in the presence of sparsity by distinguishing between structural sparsity and activation sparsity. It also naturally accounts for noise and accommodates diverse encodings (e.g. fixed-width binary, spike trains, etc) to offer a ‘common currency’ for evaluating innovation across diverse computing Paradigms.

Andrew Lin, Daniel Querrey, Eric McGonagle, John Langs, Nai Yun Wu, John Ho, Nick Almeter, Matthew Fisher, Utsawb Lamichhane, Praket Desai, David Mascarenas, Tracy Hammond; Texas A&M University & Los Alamos

Neuromorphic (event-based) cameras capture visual information as asynchronous streams of per-pixel intensity changes, offering high temporal resolution and reduced redundancy compared to frame-based sensors. Despite these advantages, the sparse and asynchronous nature of event data makes real-time inspection and interpretation challenging, limiting effective use during development, debugging, and onboarding. This paper presents NOVA (Neuromorphic Optics and Visualization Application), an integrated software system for real-time visualization, streaming, and interaction with neuromorphic event data. NOVA provides a GPU-accelerated pipeline supporting both live camera input and offline datasets, with native compatibility for modern formats and sustained high-throughput operation. A central feature is a 3D spatiotemporal visualization that represents spatial position and time simultaneously, enabling users to observe motion patterns and temporal structure that are difficult to perceive in conventional 2D views. The system also incorporates Digital Coded Exposure reconstruction to generate frame-like representations alongside raw event streams, supporting intuitive interpretation. Designed with a modular architecture and task-oriented interface, NOVA emphasizes performance, extensibility, and usability across research, development, and educational contexts. Deployment experiences and early user observations suggest that enhanced visualization and interactive temporal controls improve users’ ability to reason about event data and accelerate exploratory workflows. NOVA demonstrates how human-centered tooling can reduce barriers to working with neuromorphic sensors and provides a foundation for future research on visualization and interpretation of asynchronous visual data.

Felix Wang, Bradley Theilman, Fred Rothganger, William Severa, Craig Vineyard and James Aimone

Alex Fulleda-Garcia, Saray Soldado-Magraner and Josep Maria Margarit-Taulé

Spiking neural networks (SNNs) enable low-power, event-driven processing, but common neuron models often trade off gradient-based training, dynamical richness and spike sparsity limiting their quality-energy performance on temporal tasks. We present a gradient-trainable multi-timescale spiking-neuron framework that provides controllable firing behavior within a single model, and is amenable to efficient neuromorphic realization. Feedforward networks are evaluated on long-horizon chaotic Mackey–Glass time-series regression against leaky integrate-and-fire (LIF) and an adaptive LIF baselines. Our approach outperforms both LIF and adaptive LIF accuracies while yielding substantially sparser spiking from both communication and compute perspectives.

Ashish Gautam, Prasanna Date, Shruti Kulkarni, Ian Mulet, Kevin Zhu, Robert Patton and Thomas Potok

Spiking Neural Networks (SNNs) are computational models inspired by the event-driven communication and con- nectivity patterns of biological neural circuits. They enable high energy efficiency and natural support for diverse architectures ranging from layered networks to small-world and graph- structured topologies. In this work, we introduce NeuroCoreX, an open-source, FPGA-based spiking neural network emulator that provides real-time, on-chip learning and flexible network organization. NeuroCoreX supports both feedforward sensory inputs streamed directly from sensors or PCs via UART and recurrent on-chip connectivity, enabling simultaneous process- ing and learning from external stimuli and internal network dynamics—capabilities rarely available in existing FPGA SNN platforms. The system implements a Leaky Integrate-and-Fire (LIF) neuron model with current-based synapses and supports pair-based STDP learning on both feedforward and recurrent synapses. A lightweight Python interface enables interactive configuration, live monitoring, weight read-back, and experiment control. Importantly, NeuroCoreX is tightly integrated with the SuperNeuroMAT simulator, allowing SNN models to be transferred seamlessly from software to hardware for hardware- in-the-loop development. By combining real-time plasticity, flex- ible connectivity, and an open-source VHDL implementation, NeuroCoreX provides an extensible and accessible platform for neuromorphic research, algorithm–hardware co-design, and energy-efficient edge intelligence.

Paul Hueber, Luca Peres, Florian Pitters, Alejandro Gloriani and Oliver Rhodes

Johannes Gebert, Qifeng Pan, Lukas Stockmann, Hartwig Anzt and Christian Mayr

Brain-inspired integrated circuits in 2026 are a future high-performance computing (HPC) technology, seemingly ready for industrialization.

They demonstrated support for AI through a hardware approach and traditional algorithms commonly used in HPC. However, the community needs to determine whether these proofs of concept translate into readily usable HPC software. On the hardware side, we may have to cherry-pick the best suitable brain-inspired features and combine them with, e.g., sufficiently fast interconnects and programmability to actually outperform current HPC software and hardware stacks.

Performance and energy efficiency are two significant concerns driving capital and operational expenses, as well as returns on investment, and hence the deployment of HPC systems. However, they are not exclusive. IT security, multi-tenancy, and spare parts are just a few examples that may seem mundane from a neuromorphic perspective, but are mandatory for HPC systems.

The following paper presents the perspective of a high-performance computing center eager to adopt promising brain-inspired technologies and to serve the academic and industrial communities.

Brian Ezinwoke and Oliver Rhodes

Modern high-frequency trading environments are characterized by sudden price spikes that present both risk and opportunity, yet conventional financial models often struggle to capture the required fine temporal structure. Spiking Neural Networks (SNNs) offer a biologically inspired framework well-suited to these challenges due to their natural ability to process discrete events and preserve millisecond-scale timing. This work investigates the application of SNNs to high-frequency price-spike forecasting, enhancing performance via robust hyperparameter tuning with Bayesian Optimization. To address the inherent difficulty of tuning unsupervised Spike-Timing-Dependent Plasticity (STDP) for non-stationary data, we introduce a novel objective, Penalized Spike Accuracy (PSA), designed to align a network's predicted spike rate with empirical market event frequencies. By evaluating an extended architecture featuring explicit inhibitory competition and multiple temporal lags on microsecond-precision stock data, we demonstrate that PSA-optimized models achieve superior risk-adjusted returns when compared to both supervised backpropagation alternatives and standard accuracy-tuned benchmarks. These results suggest that task-specific tuning of spiking dynamics offers a viable methodology for training event-driven algorithms for financial time-series, inviting further exploration into the inviting further exploration into the utility of unsupervised plasticity for high-dimensional temporal data.

Ian Mulet, Derek Gobin, Ashish Gautam, Kevin Zhu, Prasanna Date, Shruti Kulkarni, Seung-Hwan Lim, Guojing Cong, Maryam Parsa, Thomas Potok and Catherine Schuman

Predicting properties of inorganic materials is a heavily researched topic, with several new prediction approaches emerging as competitors. One such competitor is graph neural networks, which leverage the structure of the graph to aid in the prediction process. In this work, we propose integration of neuromorphic computation into the graph neural network pipeline. We call this approach Neuromorphic Graph Learning (NGL). We utilize the NGL approach to leverage evolutionary algorithms and a novel Spike Pipeline for Raster Analysis (SPIRE) for the prediction of band gap in inorganic materials.

Lyes Khacef, Philipp Weidel, Susumu Hogyoku, Harry Liu, Claire Alexandra Bräuer, Shunsuke Koshino, Takeshi Oyakawa, Vincent Parret, Yoshitaka Miyatani, Mike Davies and Mathis Richter

Fall detection for elderly care using non-invasive vision-based systems remains an important yet unsolved problem. Driven by strict privacy requirements, inference must run at the edge of the vision sensor, demanding robust, real-time, and always-on perception under tight hardware constraints. To address these challenges, we propose a neuromorphic fall detection system that integrates the Sony IMX636 event-based vision sensor with the Intel Loihi 2 neuromorphic processor via a dedicated FPGA-based interface, leveraging the sparsity of event data together with near-memory asynchronous processing. Using a newly recorded dataset under diverse environmental conditions, we explore the design space of sparse neural networks deployable on a single Loihi 2 chip and analyze the tradeoffs between detection F1 score and computational cost. Notably, on the Pareto front, our LIF-based convolutional SNN with graded spikes achieves the highest computational efficiency, reaching a 55x synaptic operations sparsity for an F1 score of 58%. The LIF with graded spikes shows a gain of 6% in F1 score with 5x less operations compared to binary spikes. Furthermore, our MCUNet feature extractor with patched inference, combined with the S4D state space model, achieves the highest F1 score of 84% with a synaptic operations sparsity of 2x and a total power consumption of 90 mW on Loihi 2. Overall, our smart security camera proof-of-concept highlights the potential of integrating neuromorphic sensing and processing for edge AI applications where latency, energy consumption, and privacy are critical.

Ruyin Wan, George Em Karniadakis, and Panos Stinis

Spiking neural networks (SNNs) offer energy-efficient computation but face fundamental challenges in continuous regression due to non-differentiable spike dynamics. In this talk, we present a fully differentiable spiking framework based on quadratic integrate-and-fire (QIF) neurons, where spikes are represented as phase-based transitions rather than discrete events. This formulation enables exact gradient computation via standard backpropagation and eliminates surrogate gradients. We demonstrate improved accuracy and stability performance on spiking regression and physics-informed learning tasks, highlighting the potential of differentiable SNNs for scientific machine learning.

Yannik Stradmann, Johannes Schemmel, Mihai A. Petrovici and Laura Kriener

Sensory processing on neuromorphic hardware typically relies on event-based sensors or prior conversion of signals into spikes. In this talk, we present an alternative approach using the BrainScaleS-2 mixed-signal system: direct analog signal injection into on-chip neuron circuits enables efficient near-sensor processing without prior analog-to-digital or digital-to-analog conversion. Leveraging the platform’s 1000-fold acceleration factor, we implement a spiking neural network that transforms interaural time differences into a spatial representation to predict sound source location. We demonstrate a fully on-chip pipeline—from continuous microphone input, through accelerated neural processing, to actuator control—by localizing transient noise sources and aligning a servo motor in real time.

Joscha Ilmberger and Johannes Schemmel

The BrainScaleS-2 SoC integrates analog neuron and synapse circuits with digital periphery, including two CPUs with SIMD extensions. Each ASIC is connected to a Node-FPGA, providing experiment control and Ethernet connectivity. This work details the scaling of the compute substrate through FPGA-based interconnection via an additional Aggregator unit. The Aggregator provides up to 12 transceiver links to a backplane of Node-FPGAs, as well as 4 transceiver lanes for further extension. Two such interconnected backplanes are integrated into a standard 19in rack case with 4U height together with an Ethernet switch, system controller and power supplies. For all spike rates, chip-to-chip latencies—consisting of four hops across three FPGAs—below 1.3μs are achieved within each backplane.

Elias Arnold, Yannik Stradmann, Joscha Ilmberger, Eric Müller and Johannes Schemmel

We present the first demonstration of a four-chip BrainScaleS-2 neuromorphic system showcasing spiking neural network model inference and hardware-in-the-loop training. Building on several years of single-chip BrainScaleS-2 availability, the newly commissioned system uses a hierarchical communication fabric linking an initial set of four Brain ScaleS-2 ASICs. We evaluate this architecture using a spiking neural network whose hidden layer is distributed across three chips while placing the output layer on a fourth chip, thus exceeding the resource limits of any previously available BrainScaleS-2 substrate. We report about stable experiment execution and gradient-based training using surrogate gradients with the MNIST dataset. This talk introduces the BrainScaleS-2 multi-chip system as a platform for scalable analog neuromorphic computing.

Lukas König, Manuel Kuhn, David Kappel and Anand Subramoney

Hamed Poursiami, Shay Snyder, Guojing Cong, Thomas Potok and Maryam Parsa

Graph Neural Networks (GNNs) offer high accuracy but incur computational costs that limit scalability on edge devices. We present VS-Graph, a vector-symbolic framework that bridges the gap between the efficiency of Hyperdimensional Computing (HDC) and the expressive power of message passing. By introducing Spike Diffusion for topology-driven identification and Associative Message Passing in high-dimensional space, VS-Graph achieves accuracy competitive with modern GNNs without gradient-based optimization. Our results demonstrate a training speedup of up to 450× over GNNs and a 4–5% accuracy improvement over prior HDC baselines, while maintaining robustness even under aggressive dimensionality reduction.

So Hyeon Park and Woo Jong Yu

Ryan O'Loughlin, Bakhrom Oripov, Nick Skuda Skuda, Noah Chongsiriwatana, Ian Whitehouse, Wolfgang Losert, Bradley Hayes, Adam McCaughan and Sonia Buckley