NEUROTECH event: Future Application Directions for Neuromorphic Computing Technologies: agenda and registration (free, but mandatory). A half-day event with special focus on potential application of neuromorphic computing.
Getting to the venue:
the nearest tram stop to the meeting venue is "Heidelberg Bunsengymnasium" (marked in the map linked above) [online timetable]https://reiseauskunft.bahn.de//bin/query.exe/en?Z=Neuenheim+Bunsengymnasium,+Heidelberg), provided by German Railway. Here you can also buy tickets online
As predicted by John Hennessy, there has been a “Cambrian explosion” of computing architectures as Moore’s Law scaling has broken down. This is most obvious in the new field of AI hardware, where the competition to develop and commercialize chips for deep learning training and inference is particularly strong. There is no consensus as to whether the same architectures will be appropriate for data-center computation and edge computation, although some practitioners are starting to differentiate architectures on the basis of whether inputs (typically, images or video frames) can be accumulated before processing (allowing for very large memory read and write blocks and large matrix multiplications); or whether the task demands that each frame must be processed in real time (so-called “Batch = 1” processing).
In this presentation we show that many real-world tasks are in fact “Batch << 1” operations. For example, in the case of a forward-facing video camera in a self-driving car application, the similarity between successive frames is very high, and increases as the frame rate and resolution of the video increase; a 240fps 1080p camera will typically have well over 99% of pixels unchanged between successive frames. The same high correlation between successive samples applies in other real-world workloads such as conversational audio processing.
Exploiting the correlation of input streams can lead to very efficient processing (as shown in video compression techniques such as H.264 / MPEG-4). However, it requires significantly different processing architectures, chief among which is the necessity to maintain system state in memory between inputs.
We will show that neuromorphic architectures intrinsically implement the most important features of a ‘Batch << 1” architecture, and are very well suited to edge processing. We will describe a new architecture – NeuronFlow - which is optimized for this purpose, and present results from GrAIOne, the first chip manufactured to implement this architecture. Early results show a significant processing advantage in terms of both latency and power consumption.
Jonathan Tapson (GrAI Matter Labs)
17:15‑17:35 (20+5 min)
Relational Neurogenesis for Lifelong Learning Agents
Intel Loihi platform tutorial (Lecture style. To follow along from your own laptop your need to engage with Intel’s Intel’s Neuromorphic Research Community beforehand (email firstname.lastname@example.org for more information).